Researchers at Stanford University have come up with a new high-rise chip that is “smaller, faster, cheaper – and taller”, owing to the stacking of requisite components.
The IEEE International Electron Devices Meeting which was held at San Francisco, between December 15th and 17th, witnessed the team present a paper about the skyscraper chip’s architecture.
Headed by Subhasish Mitra, associate professor of electrical engineering and of computer science, and H.-S. Philip Wong, the Williard R. and Inez Kerr Bell Professor in Stanford’s School of Engineering, the team utilises three breakthroughs, explains the news release announcing the breakthrough:
First, is a new technology for creating transistors, those tiny gates that switch electricity on and off to create digital zeroes and ones.
Second is a new type of computer memory that lends itself to multi-story fabrication.
Third is a technique to build these new logic and memory technologies into high-rise structures in a radically different way than previous efforts to stack chips.
“This research is at an early stage, but our design and fabrication techniques are scalable,” Mitra said. “With further development this architecture could lead to computing performance that is much, much greater than anything available today.”
The prototype chip revealed at IEDM shows how to put logic and memory together into three-dimensional structures that can be mass-produced, Wong said. “Paradigm shift is an overused concept, but here it is appropriate,” Wong noted. “With this new architecture, electronics manufacturers could put the power of a supercomputer in your hand.”
Researchers on the project and Ph.D candidate in Stanford’s Department of Electrical Engineering, Max Shulaker and Tony Wu, created the techniques behind the four-story high-rise chip unveiled at the conference.
“The slowest part of any computer is sending information back and forth from the memory to the processor and back to the memory. That takes a lot of time and lot of energy,” Shulaker told Computerworld. “If you look at where the new exciting apps are, it’s with big data… For these sorts of new applications, we need to find a way to handle this big data.”
“People talk about the Internet of Things, where we’re going to have millions and trillions of sensors beaming information all around,” surmises Shulaker. “You can beam all the data to the cloud to organize all the data there, but that’s a huge data deluge. You need [a chip] that can process on all this data… You want to make sense of this data before you send it off to the cloud.”
Although efforts to stack silicon chips earlier did save space but not avoid digital traffic jams caused by the connectivity by wires unlike something called ‘nanoscale elevators’ in the Stanford design.
Professors Krishna Saraswat and Yoshio Nishi of Stanford University collaborated in the project.
Read more here.
(Image credit: Stanford University)
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