Researchers at the Belgian semiconductor research hub imec have introduced a NAND-DRAM hybrid memory architecture, reportedly the first three-dimensional (3D) implementation of charge-coupled device (CCD) technology designed for memory applications. This development aims to address the current memory wall in artificial intelligence (AI) computing, where processing units such as GPUs and accelerators face delays due to inadequate memory bandwidth and power efficiency.
The new architecture merges the speed and rewritability of DRAM with the density and efficiency typically associated with NAND storage. Historically, CCD technology has been utilized in digital cameras, video equipment, and scientific imaging, but imec’s innovation repurposes it for advanced memory functions.
The 3D CCD architecture allows for vertical stacking of memory cells, unlike conventional DRAM, which arranges cells on a flat plane. This vertical arrangement reduces manufacturing costs and leakage, overcoming limitations previously encountered with DRAM technology. The design incorporates Indium Gallium Zinc Oxide (IGZO) as a replacement for silicon, promising decreased leakage and improved data retention in the process.
Imec has demonstrated charge transfer speeds exceeding 4 MHz with its prototype, albeit currently utilizing a limited number of stacked layers. The architecture holds potential for scalability similar to NAND technology, where existing commercial chips exceed 200 layers in stacking.
According to Maarten Rosmeulen, Program Director for Storage Memory at imec, the architecture’s design enables block-level data access as opposed to the byte-addressable nature of traditional DRAM, making it more suitable for modern AI workloads. Rosmeulen stated that the new device can serve as buffer memory integrated into a 3D NAND Flash string architecture, optimizing cost-effectiveness and bit density.
The hybrid architecture is expected to deliver improved endurance and reduced wear, which could prove beneficial for AI training and inference tasks moving forward. Imec has plans to position the architecture as a Compute Express Link (CXL) Type-3 device, facilitating connections between GPUs, CPUs, and accelerators—an important factor as AI models expand beyond the capabilities of local GPU resources.
While the prototype presents significant advancements, imec acknowledges several challenges, including thermal behavior, layer count scaling, and practical integration into existing systems. If these hurdles are cleared successfully, the hybrid architecture may contribute to lowering the substantial costs associated with DRAM in AI infrastructure.
