IBM has announced the creation of the world’s first sub-1 nanometer (nm) chip, utilizing its new “nanostack” architecture. This advancement allowed IBM to fabricate a functioning 7 angstrom (0.7 nm) chip, marking a significant enhancement over its existing 2 nm design.
The new chip boasts twice the transistor density of IBM’s previous 2 nm model, with nearly 100 billion transistors packed into a chip the size of a human fingernail. The company claims that this additional density could provide up to 50% more performance or 70% greater energy efficiency compared to its 2 nm node chips.
Jay Gambetta, director of IBM Research, stated that the new architecture opens possibilities for a future where computing is more powerful without proportional increases in energy usage. The nanostack architecture builds on IBM’s nanosheet transistor technology, featuring vertically stacked and staggered transistors.
Each transistor comprises three nanosheet elements, approximately five nanometers thick, with about nine nanometers of spacing between them. Each nanosheet consists of 15 rows of silicon atoms, highlighting the engineering precision involved in the design.
IBM anticipates that nanostack chips will enter mass production within roughly five years. Rapidus, a Japanese chipmaker that is collaborating with IBM, plans to start producing 2 nm chips at scale by the second half of 2027, suggesting a competitive timeframe in chip production innovation.
IBM will provide further details regarding its commercialization plans in the future. The company asserted that its new architecture would pave the way for chipmakers to develop more powerful and efficient silicon for at least the next decade.
