PCI-SIG has released draft 0.5 of the PCIe 8.0 specification, which details a significant increase in data throughput and bandwidth capabilities. PCIe 8.0 offers a maximum data rate of 256 GT/s and up to 1 TB/s of raw bi-directional bandwidth through 16x lane configurations.
The new standard provides eight times the raw data rate and bandwidth compared to PCIe 5.0. PCIe 8.0 employs PAM4 signaling technology and is designed to be backward-compatible with existing PCIe systems.
PCI-SIG has stated that it is evaluating new connector technologies for PCIe 8.0. The specification aims to enhance bandwidth and reduce power consumption through protocol enhancements. It aligns with PCI-SIG’s roadmap to double I/O bandwidth every three years.
The bandwidth breakdown across various lane configurations is as follows: x1 offers 64 GB/s; x2 provides 128 GB/s; x4 allows 256 GB/s; x8 provides 512 GB/s; and x16 delivers 1024 GB/s. At x1 mode, PCIe 8.0 achieves the bandwidth of PCIe 4.0 in x16 mode and PCIe 5.0 in x8 mode. In x2 mode, it matches PCIe 5.0’s full bandwidth. Additionally, at x4 mode, it equals PCIe 6.0’s full capability.
Draft 0.5 was released ahead of schedule for member review, incorporating feedback from draft 0.3 released in September 2025. PCIe 8.0 is on track for full release by 2028.
The objectives of PCIe 8.0 include achieving optimal latency, forward error correction (FEC), and ensuring reliability while maintaining backward compatibility. This standard targets data-intensive markets such as artificial intelligence, data centers, high-speed networking, edge computing, and quantum computing.
