Update: This article was updated on July 23, 2025, to include a clarification from Nvidia. The text has been revised to more accurately reflect that CUDA support for RISC-V is an ongoing development effort without a confirmed release timeline.
Nvidia announced it is working to bring CUDA platform support to the RISC-V instruction set architecture (ISA) at the 2025 RISC-V Summit in China, with the goal of enabling RISC-V to serve as a main processor for CUDA-based systems.
Nvidia has clarified that support for CUDA with RISC-V is a work in progress and has not announced a timeline for its release. The company noted that the project’s completion depends on continued collaboration with the broader RISC-V ecosystem and the future availability of data-center-class RISC-V CPU platforms.
This development is intended to allow RISC-V to function as the primary processor for systems utilizing CUDA, a role previously exclusive to x86 and Arm core architectures. While immediate integration into hyperscale datacenters is not anticipated, the vision for this compatibility also extends to CUDA-enabled edge devices, specifically Nvidia’s Jetson modules.
Exciting news from #RISCVSummitChina, as Frans Sijstermans from NVIDIA announces CUDA is coming to RISC-V! This port will enable a RISC-V CPU to be the main application processor in a CUDA-based AI system.#RISCV #RISCVEverywhere pic.twitter.com/08C2ghPHq9
— RISC-V International (@risc_v) July 18, 2025
Nvidia’s engagement with RISC-V appears significant, evidenced by Frans Sijsterman, Vice President of Hardware Engineering at Nvidia, delivering the keynote address at the RISC-V Summit China.
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Sijsterman’s presentation detailed a proof-of-concept for the operational integration of CUDA components with RISC-V. A representative diagram showcased a typical configuration where the Graphics Processing Unit (GPU) manages parallel workloads. Concurrently, a RISC-V Central Processing Unit (CPU) executes CUDA system drivers, application logic, and the operating system. This arrangement facilitates the CPU’s full orchestration of GPU computations within the CUDA environment. The specific nature of these workloads, while aligned with Nvidia’s focus on Artificial Intelligence, was not explicitly confirmed as AI-related.
The depicted system also incorporated a Data Processing Unit (DPU) dedicated to handling networking tasks. This comprehensive configuration, comprising GPU for compute, CPU for orchestration, and DPU for data movement, indicates Nvidia’s strategic direction towards creating heterogeneous compute platforms. Within this framework, a RISC-V CPU can assume a central role in managing workloads, while Nvidia’s GPUs, DPUs, and networking chips manage other functions. This move bridges Nvidia’s proprietary CUDA stack with an open architecture.
The integration of RISC-V would expand CUDA’s applicability within systems that prefer open instruction sets or require tailored processor implementations. This includes custom silicon designs. Additionally, the inclusion of RISC-V would also enhance the options available to Nvidia Jetson developers who are working with specialized or embedded computing platforms.
